Responsibilities: Create UVM chip level verification environments for multiple FPGAs Develop reusable agents, top level testbench modules and environments Develop scoreboards and predictors based upon DUT requirements Define and implement functional coverage model based upon DUT requirements Verification of control and data plane functionality Verify existing interface protocol modules retargeted to different FPGA vendor/architectures.
Role might additionally require some limited module level design work in VHDL Document and execute test plan, and debug module
– and chip-level tests Develop and run regression tests Minimum Qualifications: Expertise in UVM and SystemVerilog required FPGA/ASIC verification experience.
Self-motivated, strong communications skills, schedule-conscious, and team-oriented Bachelors, BSEE or MSEE preferred
Apply Now: https://ift.tt/2RWOE0K
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